In recent years, many semiconductor memory devices are proposed in which memory cells are disposed three-dimensionally to increase the degree of integration of memory.
For example, a nonvolatile semiconductor memory device includes a memory region having memory cells arranged therein, and a peripheral region positioned in the periphery of the memory region. Further, the structure of this nonvolatile semiconductor memory device includes a plurality of conductive layers (silicon (Si)) and insulating layers (silicon oxide (SiO2)) stacked in the memory region and the peripheral region, and a column-shaped semiconductor layer (silicon (Si)) extending so as to penetrate these conductive layers and insulating layers. The conductive layers include a stepped portion formed in a stepped shape in a peripheral region thereof to allow contact with wiring in an upper layer. Moreover, in the memory region, the conductive layers function as control gates of the memory transistors (memory cells) and the semiconductor layer functions as a channel (body) of the memory transistors (memory cells).
However, since the above-described conductive layers and insulating layers have etching rates that differ greatly, it is difficult to form holes penetrating the conductive layers and insulating layers in one lot. Furthermore, there is a need to prevent faults from being generated in the stepped portion during manufacturing processes.